1. Field of the Invention
This invention generally relates to computer compilers and, more particularly, to a method that permits an optimizing compiler to generate more efficient code for computers that have dissimilar register spaces. The invention has specific application to optimizing compilers for reduced instruction set computers (RISC) but could be used with advantage in any compiler.
2. Description of the Prior Art
There currently exists a need for a technique that may be used to improve the quality of the object code produced by a compiler. The technique should apply to a machine that has multiple register spaces, with the properties that some operations can only be done in one of the spaces, some can be done in either, and it is time-consuming to move data from one space to another. Examples of register spaces are general purpose registers (GPRs), floating point registers (FPRs) and condition registers (CRs). As an example of a time-consuming move, on the IBM Systems 370 (S/370) series of computers, and in many other computers, the only way to move data between a GPR and an FPR is to go through storage; i.e., to execute a Store Float followed by a Load or a Store followed by a Load Float.